ET
2002
13 years 11 months ago
2002
The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test ar...
VTS
2007
IEEE
14 years 5 months ago
2007
IEEE
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...