Reusing Scan Chains for Test Pattern Decompression

The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.

• Type: Journal
• Year: 2002
• Where: ET
• Authors: Rainer Dorsch, Hans-Joachim Wunderlich
• Keywords: Certain Core, Compressed Representation, ET 2002, External Tester