Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

24

ET
2002

favoriteEmaildiscussreport

77views more ET 2002»

Reusing Scan Chains for Test Pattern Decompression

13 years 11 months ago

Reusing Scan Chains for Test Pattern Decompression

Download www.iti.uni-stuttgart.de

The paper presents a method for testing a system-on-achip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.

Rainer Dorsch, Hans-Joachim Wunderlich

Real-time Traffic

Certain Core | Compressed Representation | ET 2002 | External Tester |

claim paper

Related Content

» Efficient SpaceTime Compression to Reduce Test Data Volume and Testing Time for IP Cores

» Frugal linear networkbased test decompression for drastic test cost reductions

» Test Resource Partitioning and Reduced PinCount Testing Based on Test Data Compression

» Deterministic Test Vector CompressionDecompression for SystemsonaChip Using an Embedded Pr...

» Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

» MatrixBased Test Vector Decompression Using an Embedded Processor

» A selective patterncompression scheme for power and testdata reduction

» Adaptive Diagnostic Pattern Generation for Scan Chains

» Scan chain clustering for test power reduction

Post Info
More Details (n/a)

Added	18 Dec 2010
Updated	18 Dec 2010
Type	Journal
Year	2002
Where	ET
Authors	Rainer Dorsch, Hans-Joachim Wunderlich

Comments (0)