Sciweavers

ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
14 years 6 months ago
A low-power clock frequency multiplier
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao