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JILP
2000
109views more  JILP 2000»
14 years 11 days ago
Dynamic Register Renaming Through Virtual-Physical Registers
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instructio...
Teresa Monreal, Antonio González, Mateo Val...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
14 years 5 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...