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FPL
2004
Springer
106views Hardware» more  FPL 2004»
14 years 4 months ago
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
Leandro Möller, Ney Laert Vilar Calazans, Fer...
FPL
2004
Springer
81views Hardware» more  FPL 2004»
14 years 4 months ago
Design and Implementation of the Memory Scheduler for the PC-Based Router
Tomás Marek, Martin Novotný, Ludek C...
FPL
2004
Springer
142views Hardware» more  FPL 2004»
14 years 4 months ago
IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter
In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth...
Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred G...
FPL
2004
Springer
103views Hardware» more  FPL 2004»
14 years 4 months ago
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne L...
FPL
2004
Springer
89views Hardware» more  FPL 2004»
14 years 4 months ago
HW/SW Co-design by Automatic Embedding of Complex IP Cores
Complex SoC and platform-based designs require integration of configurable IP cores from multiple sources. Even automatic compilation flows from a high-level description to HW/SW s...
Holger Lange, Andreas Koch
FPL
2004
Springer
95views Hardware» more  FPL 2004»
14 years 4 months ago
Improving FPGA Performance and Area Using an Adaptive Logic Module
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay...
Michael Hutton, Jay Schleicher, David M. Lewis, Br...
FPL
2004
Springer
87views Hardware» more  FPL 2004»
14 years 4 months ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood
FPL
2004
Springer
101views Hardware» more  FPL 2004»
14 years 4 months ago
Automatic Creation of Reconfigurable PALs/PLAs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
Mark Holland, Scott Hauck
FPL
2004
Springer
67views Hardware» more  FPL 2004»
14 years 4 months ago
A Key Management Architecture for Securing Off-Chip Data Transfers
Jonathan Graf, Peter M. Athanas