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FPL
2004
Springer
75views Hardware» more  FPL 2004»
14 years 4 months ago
Multiple Restricted Multiplication
Abstract. This paper focuses on a class of problem relating to the multiplication of a single number by several coefficients that, while not constant, are drawn from a finite set ...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
FPL
2004
Springer
205views Hardware» more  FPL 2004»
14 years 4 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
FPL
2004
Springer
125views Hardware» more  FPL 2004»
14 years 4 months ago
SoftSONIC: A Customisable Modular Platform for Video Applications
This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application developraising the level of abstraction and facilitating design reus...
Tero Rissa, Peter Y. K. Cheung, Wayne Luk
FPL
2004
Springer
74views Hardware» more  FPL 2004»
14 years 4 months ago
A Structured Methodology for System-on-an-FPGA Design
Abstract. Increasing logic resources coupled with a proliferation of integrated performance enhancing primitives in high-end FPGAs results in an increased design complexity which r...
N. Pete Sedcole, Peter Y. K. Cheung, George A. Con...
FPL
2004
Springer
171views Hardware» more  FPL 2004»
14 years 4 months ago
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Field Programmable Gate Arrays (FPGAs) can be used in Intrusion Prevention Systems (IPS) to inspect application data contained within network flows. An IPS operating on high-speed...
David V. Schuehler, John W. Lockwood
FPL
2004
Springer
83views Hardware» more  FPL 2004»
14 years 4 months ago
System-Level Modeling of Dynamically Reconfigurable Co-processors
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the perfor...
Yang Qu, Kari Tiensyrjä, Kostas Masselos
FPL
2004
Springer
103views Hardware» more  FPL 2004»
14 years 4 months ago
JHDLBits: The Merging of Two Worlds
Abstract. This paper introduces JHDLBits, the integration of two prominent FPGA design tools: JHDL and JBits. JHDLBits offers the low-level access and control provided by JBits wi...
Alexandra Poetter, Jesse Hunter, Cameron Patterson...
FPL
2004
Springer
112views Hardware» more  FPL 2004»
14 years 4 months ago
Automating the Layout of Reconfigurable Subsystems via Template Reduction
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
Shawn Phillips, Akshay Sharma, Scott Hauck
FPL
2004
Springer
117views Hardware» more  FPL 2004»
14 years 4 months ago
Flow Monitoring in High-Speed Networks with 2D Hash Tables
Abstract. Flow monitoring is a required task for a variety of networking applications including fair scheduling and intrusion/anomaly detection. Existing flow monitoring techniques...
David Nguyen, Joseph Zambreno, Gokhan Memik
FPL
2004
Springer
98views Hardware» more  FPL 2004»
14 years 4 months ago
Power-Driven Design Partitioning
In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficienc...
Rajarshi Mukherjee, Seda Ogrenci Memik