This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
A Customized Reconfigurable Interconnection Network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirem...
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
Brian Leung, Yan Pan, Chris Schroeder, Seda Ogrenc...
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
This paper presents SPA (Simple Power Analysis) attacks against public-key cryptosystems implemented on an FPGA platform. The SPA attack investigates a power waveform generated by...
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfi...
An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which a...
Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kam...
Traditional microprocessor-based solutions are insufficient to serve the dynamic throughput demands of real-time scalable multimedia processing systems. This paper introduces a Po...