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    DAC
    2004
    ACM
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    Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
    15 years 15 days ago
    Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
    Download  vlsi.ece.wisc.edu
    With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
    Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
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