GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
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GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE