GLVLSI
2009
IEEE
14 years 6 months ago
2009
IEEE
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
GLVLSI
2009
IEEE
14 years 6 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
GLVLSI
2009
IEEE
14 years 6 months ago
2009
IEEE
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
GLVLSI
2009
IEEE
14 years 6 months ago
2009
IEEE
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...
GLVLSI
2009
IEEE
14 years 6 months ago
2009
IEEE
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
GLVLSI
2009
IEEE
2009
IEEE
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
14 years 6 months ago
This paper discusses the impact of migrating from 2-D to 3-D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3-...