MICRO
1994
IEEE
14 years 25 days ago
1994
IEEE
ITC
1994
IEEE
14 years 25 days ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
ITC
1994
IEEE
14 years 25 days ago
1994
IEEE
For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavi...
ITC
1994
IEEE
14 years 25 days ago
1994
IEEE
ITC
1994
IEEE
14 years 25 days ago
1994
IEEE
: The IC test industry has struggled .for more than 30years to establish a test approach that would guarantee a low defect level to the customer. Wepropose a comprehensive strategy...
ITC
1994
IEEE
14 years 25 days ago
1994
IEEE
ISMVL
1994
IEEE
14 years 25 days ago
1994
IEEE
ISMVL
1994
IEEE
14 years 25 days ago
1994
IEEE
Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over "weakened" state values. This technique has long been practice...
ISMVL
1994
IEEE
14 years 25 days ago
1994
IEEE
The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks...
ISMVL
1994
IEEE
14 years 25 days ago
1994
IEEE
We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a