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MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
14 years 25 days ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
MICRO
1993
IEEE
97views Hardware» more  MICRO 1993»
14 years 25 days ago
Register renaming and dynamic speculation: an alternative approach
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...
Mayan Moudgill, Keshav Pingali, Stamatis Vassiliad...
MICRO
1993
IEEE
131views Hardware» more  MICRO 1993»
14 years 25 days ago
Superblock formation using static program analysis
Compile-time code transformations which expose instruction-level parallelism (ILP) typically take into account the constraints imposed by all execution scenarios in the program. H...
Richard E. Hank, Scott A. Mahlke, Roger A. Bringma...
MICRO
1993
IEEE
127views Hardware» more  MICRO 1993»
14 years 25 days ago
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
Ing-Jer Huang, Alvin M. Despain
MICRO
1993
IEEE
93views Hardware» more  MICRO 1993»
14 years 25 days ago
Speculative execution exception recovery using write-back suppression
Compiler-controlled speculative execution has been shown to be e ective in increasing the availableinstruction level parallelismILP found in non-numeric programs. An importantpr...
Roger A. Bringmann, Scott A. Mahlke, Richard E. Ha...
ITC
1993
IEEE
104views Hardware» more  ITC 1993»
14 years 25 days ago
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Built-In-Self-Test BIST for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means ...
M. F. Toner, Gordon W. Roberts
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
14 years 25 days ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...