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ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
14 years 28 days ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
ISLPED
1997
ACM
81views Hardware» more  ISLPED 1997»
14 years 28 days ago
A method of redundant clocking detection and power reduction at RT level design
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, T...
ISLPED
1997
ACM
58views Hardware» more  ISLPED 1997»
14 years 28 days ago
Exploiting the locality of memory references to reduce the address bus energy
Enric Musoll, Tomás Lang, Jordi Cortadella
ISLPED
1997
ACM
84views Hardware» more  ISLPED 1997»
14 years 28 days ago
Low-power H.263 video CoDec dedicated to mobile computing
Morgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isa...
ISLPED
1997
ACM
108views Hardware» more  ISLPED 1997»
14 years 28 days ago
Techniques for low energy software
The energy consumption of a system depends upon the hardware and software component of a system. Since it is the software which drives the hardware in most systems, decisions take...
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwi...
ISLPED
1997
ACM
85views Hardware» more  ISLPED 1997»
14 years 28 days ago
A new 4-2 adder and booth selector for low power MAC unit
Bum-Sik Kim, Dae-Hyum Chung, Lee-Sup Kim
ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
14 years 28 days ago
Analytical energy dissipation models for low-power caches
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run tim...
Milind B. Kamble, Kanad Ghose
ISLPED
1997
ACM
83views Hardware» more  ISLPED 1997»
14 years 28 days ago
A symbolic algorithm for low-power sequential synthesis
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
Balakrishna Kumthekar, In-Ho Moon, Fabio Somenzi