ASAP
1996
IEEE
14 years 28 days ago
1996
IEEE
We propose in this paper a new algorithm and architecture for performing divisions in residue number systems. Our algorithm is suitable for residue number systems with large modul...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
Informed prefetching and caching based on application disclosure of future I/O accesses (hints) can dramatically reduce the execution time of I/O-intensive applications. A recent ...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
Benchmarks are important because they provide a means for users and researchers to characterize how their workloads will perform on different systems and different system architec...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
Enterprise level web proxies relay world-wide web traffic between private networks and the Internet. They improve security, save network bandwidth, and reduce network latency. Wh...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
By providing direct data transfer between storage and client, network-attached storage devices have the potential to improve scalability for existing distributed file systems (by...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
Rate based congestion control has been considered desirable, both to deal with the high bandwidth-delay products of today's high speed networks, and to match the needs of eme...
SIGMETRICS
1997
ACM
14 years 28 days ago
1997
ACM
The Internet is a very large scale, complex, dynamical system that is hard to model and analyze. In this paper, we develop and analyze statistical models for the observed end-to-e...
ISPD
1997
ACM
14 years 28 days ago
1997
ACM
In this paper, we study optimal bu er design in high-performance VLSI systems. Speci cally, we design a bu er for a given load such that chip area and power dissipation are minima...