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MICRO
1998
IEEE
102views Hardware» more  MICRO 1998»
14 years 1 months ago
Improving I/O Performance with a Conditional Store Buffer
Lambert Schaelicke, Al Davis
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
14 years 1 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
MICRO
1998
IEEE
92views Hardware» more  MICRO 1998»
14 years 1 months ago
Predictive Techniques for Aggressive Load Speculation
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
Glenn Reinman, Brad Calder
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
14 years 1 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
MICRO
1998
IEEE
91views Hardware» more  MICRO 1998»
14 years 1 months ago
Effective Cluster Assignment for Modulo Scheduling
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...
Erik Nystrom, Alexandre E. Eichenberger
MICRO
1998
IEEE
82views Hardware» more  MICRO 1998»
14 years 1 months ago
Simple Vector Microprocessors for Multimedia Applications
Corinna G. Lee, Mark G. Stoodley
MICRO
1998
IEEE
111views Hardware» more  MICRO 1998»
14 years 1 months ago
Precise Register Allocation for Irregular Architectures
This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP registe...
Timothy Kong, Kent D. Wilken
MICRO
1998
IEEE
144views Hardware» more  MICRO 1998»
14 years 1 months ago
Analyzing the Working Set Characteristics of Branch Execution
To achieve highly accurate branch prediction, it is necessary not only to allocate more resources to branch prediction hardware but also to improve the understanding of branch exe...
Sangwook P. Kim, Gary S. Tyson
MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
14 years 1 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
MICRO
1998
IEEE
93views Hardware» more  MICRO 1998»
14 years 1 months ago
The YAGS Branch Prediction Scheme
The importance of an accurate branch prediction mechanism has been well documented. Since the
A. N. Eden, Trevor N. Mudge