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ISPD
2000
ACM
70views Hardware» more  ISPD 2000»
14 years 1 months ago
Requirements for models of achievable routing
Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
ISPD
2000
ACM
88views Hardware» more  ISPD 2000»
14 years 1 months ago
Classical floorplanning harmful?
Andrew B. Kahng
ISPD
2000
ACM
93views Hardware» more  ISPD 2000»
14 years 1 months ago
DUNE: a multi-layer gridless routing system with wire planning
Jason Cong, Jie Fang, Kei-Yong Khoo
ISPD
2000
ACM
68views Hardware» more  ISPD 2000»
14 years 1 months ago
Optimal reliable crosstalk-driven interconnect optimization
Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jin...
ISPD
2000
ACM
169views Hardware» more  ISPD 2000»
14 years 1 months ago
Aggressor alignment for worst-case coupling noise
In this paper we study signal alignment resulting in maximum peak interconnect crosstalk noise. We consider two cases. In the first one we assume that arbitrary arrival times of i...
Lauren Hui Chen, Malgorzata Marek-Sadowska
ISPD
2000
ACM
86views Hardware» more  ISPD 2000»
14 years 1 months ago
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...
Li-Fu Chang, Keh-Jeng Chang, Robert Mathews
ISPD
2000
ACM
73views Hardware» more  ISPD 2000»
14 years 1 months ago
Pseudo pin assignment with crosstalk noise control
Chin-Chih Chang, Jason Cong
ISPD
2000
ACM
124views Hardware» more  ISPD 2000»
14 years 1 months ago
A performance optimization method by gate sizing using statistical static timing analysis
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
Masanori Hashimoto, Hidetoshi Onodera
ISPD
2000
ACM
108views Hardware» more  ISPD 2000»
14 years 1 months ago
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...
Yu-Yen Mo, Chris C. N. Chu