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VTS
2000
IEEE
167views Hardware» more  VTS 2000»
14 years 1 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
VTS
2000
IEEE
99views Hardware» more  VTS 2000»
14 years 1 months ago
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
Abhijit Jas, Bahram Pouya, Nur A. Touba
VTS
2000
IEEE
94views Hardware» more  VTS 2000»
14 years 1 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
VTS
2000
IEEE
97views Hardware» more  VTS 2000»
14 years 1 months ago
A Low-Speed BIST Framework for High-Performance Circuit Testing
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
VTS
2000
IEEE
100views Hardware» more  VTS 2000»
14 years 1 months ago
Functional Memory Faults: A Formal Notation and a Taxonomy
Abstract: This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has...
A. J. van de Goor, Zaid Al-Ars
VTS
2000
IEEE
108views Hardware» more  VTS 2000»
14 years 1 months ago
High-Level Observability for Effective High-Level ATPG
This paper focuses on observability, one of the open issues in High-Level test generation. Three different approximate metrics for taking observability into account during RT-leve...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
VTS
2000
IEEE
114views Hardware» more  VTS 2000»
14 years 1 months ago
Detection of CMOS Defects under Variable Processing Conditions
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points. In this paper, the power supply transient...
Amy Germida, James F. Plusquellic
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
14 years 1 months ago
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
Li Chen, Sujit Dey
VTS
2000
IEEE
113views Hardware» more  VTS 2000»
14 years 1 months ago
Hidden Markov and Independence Models with Patterns for Sequential BIST
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Laurent Bréhélin, Olivier Gascuel, G...
VTS
2000
IEEE
70views Hardware» more  VTS 2000»
14 years 1 months ago
Thermal Testing: Fault Location Strategies
Josep Altet, Antonio Rubio, E. Schaub, Stefan Dilh...