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IOLTS
2002
IEEE
148views Hardware» more  IOLTS 2002»
14 years 1 months ago
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
The reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reco...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
IOLTS
2002
IEEE
99views Hardware» more  IOLTS 2002»
14 years 1 months ago
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
Davide Appello, Alessandra Fudoli, Vincenzo Tancor...
IOLTS
2002
IEEE
127views Hardware» more  IOLTS 2002»
14 years 1 months ago
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods
A silicon independent C-Based model of the TTP/C protocol was implemented within the EU-founded project FIT. The C-based model is integrated in the C-Sim simulation environment. T...
Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan ...
IOLTS
2002
IEEE
87views Hardware» more  IOLTS 2002»
14 years 1 months ago
BIST-Based Delay-Fault Testing in FPGAs
Miron Abramovici, Charles E. Stroud
IEEEINTERACT
2002
IEEE
14 years 1 months ago
On the Predictability of Program Behavior Using Different Input Data Sets
Smaller input data sets such as the test and the train input sets are commonly used in simulation to estimate the impact of architecture/micro-architecture features on the perform...
Wei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yu...
IEEEINTERACT
2002
IEEE
14 years 1 months ago
Code Cache Management Schemes for Dynamic Optimizers
A dynamic optimizer is a software-based system that performs code modifications at runtime, and several such systems have been proposed over the past several years. These systems ...
Kim M. Hazelwood, Michael D. Smith
IEEEINTERACT
2002
IEEE
14 years 1 months ago
Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread Integration
Embedded systems require control of many concurrent real-time activities, leading to system designs which feature multiple hardware peripherals with each providing a specific, ded...
Alexander G. Dean
ICECCS
2002
IEEE
93views Hardware» more  ICECCS 2002»
14 years 1 months ago
Mnemosyne: Designing and Implementing Network Short-Term Memory
Network traffic logs play an important role in incident analysis. With the increasing throughput of network links, maintaining a complete log of all network activity has become a...
Giovanni Vigna, Andrew Mitchel
ICECCS
2002
IEEE
79views Hardware» more  ICECCS 2002»
14 years 1 months ago
A Framework for Performability Modeling of Messaging Services in Distributed Systems
Messaging services are a useful component in distributed systems that require scalable dissemination of messages (events) from suppliers to consumers. These services decouple supp...
Srinivasan Ramani, Katerina Goseva-Popstojanova, K...
ICECCS
2002
IEEE
99views Hardware» more  ICECCS 2002»
14 years 1 months ago
Using Role-Based Modeling Language (RBML) to Characterize Model Families
Cost-effective development of large, integrated computer-based systems can be realized through systematic reuse of development experiences throughout the development process. In t...
Dae-Kyoo Kim, Robert B. France, Sudipto Ghosh, Eun...