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ISCA
2002
IEEE
68views Hardware» more  ISCA 2002»
14 years 1 months ago
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
14 years 1 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
ISCA
2002
IEEE
96views Hardware» more  ISCA 2002»
14 years 1 months ago
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste...
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 1 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
14 years 1 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 1 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 1 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
14 years 1 months ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin
IOLTS
2002
IEEE
115views Hardware» more  IOLTS 2002»
14 years 1 months ago
Analysis of SEU Effects in a Pipelined Processor
Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ...
IOLTS
2002
IEEE
103views Hardware» more  IOLTS 2002»
14 years 1 months ago
Sequential Circuits Applicable for Detecting Different Types of Faults
Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky...