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ISCAS
2002
IEEE
99views Hardware» more  ISCAS 2002»
14 years 1 months ago
An analog-to-digital converter with time-variant window
We present a first order analog-to-digital converter with time-variant window. If a DC input is applied, the converter outputs a binary sequence until the internal state enters i...
H. Imamura, Toshimichi Saito, Hiroyuki Torikai
ISCAS
2002
IEEE
190views Hardware» more  ISCAS 2002»
14 years 1 months ago
A high performance JPEG2000 architecture
—JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of ...
Kishore Andra, Chaitali Chakrabarti, Tinku Acharya
ISCAS
2002
IEEE
94views Hardware» more  ISCAS 2002»
14 years 1 months ago
Video transport over ad-hoc networks using multiple paths
Enabling video transport over ad-hoc networks is more challenging than over other wireless networks because a connection path in an ad-hoc network is highly error-prone and a path...
Shunan Lin, Yao Wang, Shiwen Mao, Shivendra S. Pan...
ISCAS
2002
IEEE
79views Hardware» more  ISCAS 2002»
14 years 1 months ago
High-speed pipelined A/D converter using time-shifted CDS technique
A time-shifted correlated double sampling (CDS) technique is used to compensate for the finite opamp dc gain in the context of a pipelined analog-to-digital converter (ADC). This...
Jipeng Li, Un-Ku Moon
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
14 years 1 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 1 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 1 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
14 years 1 months ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee