DATE
2007
IEEE
14 years 8 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
BROADNETS
2007
IEEE
14 years 8 months ago
2007
IEEE
Fast convergence to topology changes is a key requirement in modern routing infrastructure while reducing the protocol CPU overhead continues to be as important as before. In this...
GLVLSI
2008
IEEE
14 years 8 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...