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HPCA
2001
IEEE
15 years 25 days ago
Dynamic Branch Prediction with Perceptrons
This paper presents a new method for branch prediction. The key idea is to use one of the simplest possible neural networks, the perceptron as an alternative to the commonly used ...
Daniel A. Jiménez, Calvin Lin
HPCA
2001
IEEE
15 years 25 days ago
Quantifying the Impact of Architectural Scaling on Communication
Taliver Heath, Samian Kaur, Richard P. Martin, Thu...
HPCA
2001
IEEE
15 years 25 days ago
DRAM Energy Management Using Software and Hardware Directed Power Mode Control
While there have been several studies and proposals for energy conservation for CPUs and peripherals, energy optimization techniques for selective operating mode control of DRAMs ...
Victor Delaluz, Mahmut T. Kandemir, Narayanan Vija...
HPCA
2001
IEEE
15 years 25 days ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...
HPCA
2001
IEEE
15 years 25 days ago
Dynamic Thermal Management for High-Performance Microprocessors
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...
David Brooks, Margaret Martonosi
HPCA
2001
IEEE
15 years 25 days ago
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
Bart Goeman, Hans Vandierendonck, Koenraad De Boss...
HPCA
2001
IEEE
15 years 25 days ago
Call Graph Prefetching for Database Applications
Murali Annavaram, Jignesh M. Patel, Edward S. Davi...
HPCA
2001
IEEE
15 years 25 days ago
Reevaluating Online Superpage Promotion with Hardware Support
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. ...
HPCA
2001
IEEE
15 years 25 days ago
A New Scalable Directory Architecture for Large-Scale Multiprocessors
The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very la...
Manuel E. Acacio, José González, Jos...
HPCA
2001
IEEE
15 years 25 days ago
Performance of Hardware Compressed Main Memory
A new memory subsystem called Memory Expansion Technology (MXT) has been built for compressing main memory contents. MXT effectively doubles the physically available memory. This ...
Bülent Abali, Dan E. Poff, Hubertus Franke, T...