ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
? We describe a synthesis system that takes operating range constraints and inter- and intra- circuit parametric manufacturing variations into account while designing a sized and b...
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation....
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
-- We describe a new high-level compiler called Integral fordesigning system interface modules. The inputis a high-levelconcurrent algorithmic specification that can model complex ...
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
We study a new placement problem: the reproducing placement problem (RPP). In each phase a module (or gate) is decomposed into two (or more) simpler modules. The goal is nd a \go...
ICCAD
1994
IEEE
14 years 4 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...