In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design specication either as a result o...
The traditional algorithm of Stockmeyer for area minimization of slicing
oorplans has time (and space) complexity O(n2 ) in the worst case, or O(nlogn) for balanced slicing. For ...
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...
Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
Eric Lehman, Yosinori Watanabe, Joel Grodstein, He...
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
IC manufacturing process variations are typically expressed in terms of joint probability density functions (jpdf’s) or as worst case combinations/corners of the device model pa...