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    ICS
    2009
    Tsinghua U.
    105views Distributed And Parallel Com...» more  ICS 2009»
    Designing multi-socket systems using silicon photonics
    14 years 6 months ago
    Designing multi-socket systems using silicon photonics
    Download  www.cs.berkeley.edu
    Future single-board multi-socket systems may be unable to deliver the needed memory bandwidth electrically due to power limitations, which will hurt their ability to drive perform...
    Scott Beamer, Krste Asanovic, Christopher Batten, ...
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    ICS
    2009
    Tsinghua U.
    112views Distributed And Parallel Com...» more  ICS 2009»
    MPI-aware compiler optimizations for improving communication-computation overlap
    14 years 6 months ago
    MPI-aware compiler optimizations for improving communication-computation overlap
    Download  www.eecis.udel.edu
    Several existing compiler transformations can help improve communication-computation overlap in MPI applications. However, traditional compilers treat calls to the MPI library as ...
    Anthony Danalis, Lori L. Pollock, D. Martin Swany,...
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    ICS
    2009
    Tsinghua U.
    107views Distributed And Parallel Com...» more  ICS 2009»
    Pattern-based sparse matrix representation for memory-efficient SMVM kernels
    14 years 6 months ago
    Pattern-based sparse matrix representation for memory-efficient SMVM kernels
    Download  people.cs.vt.edu
    Mehmet Belgin, Godmar Back, Calvin J. Ribbens
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    ICS
    2009
    Tsinghua U.
    143views Distributed And Parallel Com...» more  ICS 2009»
    Fast and scalable list ranking on the GPU
    14 years 6 months ago
    Fast and scalable list ranking on the GPU
    Download  researchweb.iiit.ac.in
    General purpose programming on the graphics processing units (GPGPU) has received a lot of attention in the parallel computing community as it promises to offer the highest perfo...
    M. Suhail Rehman, Kishore Kothapalli, P. J. Naraya...
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    ICS
    2009
    Tsinghua U.
    144views Distributed And Parallel Com...» more  ICS 2009»
    Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
    14 years 6 months ago
    Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
    Download  www.cs.virginia.edu
    Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
    Jiayuan Meng, Kevin Skadron
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    ICS
    2009
    Tsinghua U.
    105views Distributed And Parallel Com...» more  ICS 2009»
    Cancellation of loads that return zero using zero-value caches
    14 years 6 months ago
    Cancellation of loads that return zero using zero-value caches
    Download  www.ce.chalmers.se
    The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory loc...
    Md. Mafijul Islam, Sally A. McKee, Per Stenstr&oum...
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    ICS
    2009
    Tsinghua U.
    167views Distributed And Parallel Com...» more  ICS 2009»
    High-performance regular expression scanning on the Cell/B.E. processor
    14 years 6 months ago
    High-performance regular expression scanning on the Cell/B.E. processor
    Download  domino.research.ibm.com
    Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
    Daniele Paolo Scarpazza, Gregory F. Russell
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    ICS
    2009
    Tsinghua U.
    111views Distributed And Parallel Com...» more  ICS 2009»
    Using many-core hardware to correlate radio astronomy signals
    14 years 6 months ago
    Using many-core hardware to correlate radio astronomy signals
    Download  www.astron.nl
    Rob van Nieuwpoort, John W. Romein
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    ICS
    2009
    Tsinghua U.
    151views Distributed And Parallel Com...» more  ICS 2009»
    Parametric multi-level tiling of imperfectly nested loops
    14 years 6 months ago
    Parametric multi-level tiling of imperfectly nested loops
    Download  www.cse.ohio-state.edu
    Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
    Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
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    ICS
    2009
    Tsinghua U.
    169views Distributed And Parallel Com...» more  ICS 2009»
    Combining thread level speculation helper threads and runahead execution
    14 years 6 months ago
    Combining thread level speculation helper threads and runahead execution
    Download  homepages.inf.ed.ac.uk
    With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
    Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...
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