CASES
2007
ACM
14 years 2 months ago
2007
ACM
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
MICRO
1998
IEEE
14 years 3 months ago
1998
IEEE
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
ISCA
1998
IEEE
14 years 3 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
GLVLSI
2006
IEEE
14 years 5 months ago
2006
IEEE
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...