Sciweavers

ISCAS
2005
IEEE
182views Hardware» more  ISCAS 2005»
14 years 5 months ago
Efficient search and mode prediction algorithms for motion estimation in H.264/AVC
—H.264 video coding standard adopts different coding schemes like variable block sizes and multiple reference frames for motion estimation. Hence, H.264/AVC provides gains in com...
Gwo-Long Li, Mei-Juan Chen, Hung-Ju Li, Ching-Ting...
ISCAS
2005
IEEE
181views Hardware» more  ISCAS 2005»
14 years 5 months ago
Adjustable gamma correction circuit for TFT LCD
— Gamma correction is an essential function in every display device such as CRT, plasma TV, and TFT LCD. In this paper, a new gamma correction architecture of the source drive IC...
Po-Ming Lee, Hung-Yi Chen
ISCAS
2005
IEEE
114views Hardware» more  ISCAS 2005»
14 years 5 months ago
Self-organized cortical map formation by guiding connections
We describe an algorithm for self-organizing connections from a source array to a target array of neurons that is inspired by neural growth cone guidance. Each source neuron proje...
Stanley Y. M. Lam, Bertram Emil Shi, Kwabena Boahe...
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
14 years 5 months ago
Cascode buffer for monolithic voltage conversion operating at high input supply voltages
A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed ...
Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Fr...
ISCAS
2005
IEEE
108views Hardware» more  ISCAS 2005»
14 years 5 months ago
A frequency synthesizer using two different delay feedbacks
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
Chien-Hung Kuo, Yi-Shun Shih
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
14 years 5 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
14 years 5 months ago
A low spur fractional-N frequency synthesizer architecture
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moo...
ISCAS
2005
IEEE
122views Hardware» more  ISCAS 2005»
14 years 5 months ago
Towards a rigorous formulation of the space mapping technique for engineering design
—This paper deals with the Space Mapping (SM) approach to engineering design optimization. We attempt here a theoretical justification of methods that have already proven efficie...
Slawomir Koziel, John W. Bandler, Kaj Madsen