In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-r...
This paper describes a family of high-speed Finite Impulse Response (FIR) digital filters that have been scaled across three generations of CMOS processes. The processes include c...
Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Ge...