This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...
Estimation of the area complexity of a Boolean function from its functional description is an important step towards a power estimation capability at the register transfer level (...
A 12-b 125 MSPS, digital to analog converter fabricated on a 0.6 micron single poly double metal CMOS process is presented. The design operates on supply voltages from 2.7 to 5.5 ...
The growing demand for portable electronic devices has led to an increased emphasis on power consumption within the semiconductor industry. As a result, designers are now encourag...
This paper presents an accurate switched-current multiplier, designed for 3.3V supply voltage, performing 0.625M multiplications per second with a maximum nonlinearity of 0.94%. Th...
Domine Leenaerts, G. H. M. Joordens, Johannes A. H...
-- By taking advantage of the redundancy in a 4-2 compressor, we reduce the number of transitions in carry-save adder trees that are common in large multipliers. Three new 4-2 comp...
- This paper investigates substrate noise influence on circuit performance in a variable thresholdvoltage scheme (VT scheme) where threshold voltage is dynamically varied by substr...
We present an architectural power simulation technique for PLA-based controllers. The contributions of this work are (1) a simple but ecient power characterization of PLAs; and (2...