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ISLPED
1999
ACM
70views Hardware» more  ISLPED 1999»
14 years 3 months ago
Global register allocation for minimizing energy consumption
Yumin Zhang, Xiaobo Hu, Danny Z. Chen
ISLPED
1999
ACM
177views Hardware» more  ISLPED 1999»
14 years 3 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
Vijay Sundararajan, Keshab K. Parhi
ISLPED
1999
ACM
100views Hardware» more  ISLPED 1999»
14 years 3 months ago
Ultra-low power digital subthreshold logic circuits
Hendrawan Soeleman, Kaushik Roy
ISLPED
1999
ACM
137views Hardware» more  ISLPED 1999»
14 years 3 months ago
Energy-efficient design of battery-powered embedded systems
—Energy-efficient design of battery-powered systems demands optimizations in both hardware and software. We present a modular approach for enhancing instruction level simulators ...
Tajana Simunic, Luca Benini, Giovanni De Micheli
ISLPED
1999
ACM
98views Hardware» more  ISLPED 1999»
14 years 3 months ago
Passive precharge and rippled power logic (PPRPL)
Samuel B. Schaevitz, Christopher Lin
ISLPED
1999
ACM
160views Hardware» more  ISLPED 1999»
14 years 3 months ago
Mixed-swing quadrail for low power dual-rail domino logic
This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full ad...
Bharath Ramasubramanian, Herman Schmit, L. Richard...
ISLPED
1999
ACM
91views Hardware» more  ISLPED 1999»
14 years 3 months ago
Stochastic modeling of a power-managed system: construction and optimization
-- The goal of a dynamic power management policy is to reduce the power consumption of an electronic system by putting system components into different states, each representing ce...
Qinru Qiu, Qing Wu, Massoud Pedram
ISLPED
1999
ACM
84views Hardware» more  ISLPED 1999»
14 years 3 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
ISLPED
1999
ACM
89views Hardware» more  ISLPED 1999»
14 years 3 months ago
Clock distribution using multiple voltages
Jatuchai Pangjun, Sachin S. Sapatnekar