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ISLPED
1999
ACM

An architectural solution for the inductive noise problem due to clock-gating

14 years 3 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. However, it introduces inductive noise that can limit voltage scaling. This paper introduces an architectural approach for reducing inductive noise due to clock-gating through gradual activation/deactivation of units. This technique provides a 2x reduction in ground bounce on a 16 bit ALU simulated in SPICE, while reducing simulated SPEC95 performance by less than 5% on a typical superscalar architecture.
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ISLPED
Authors Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
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