This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
We study alternatives to FM-based partitioning in the context of end-case processing for top-down standard-cell placement. The primary motivation is that small partitioning instan...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
One subtask in constraint-driven placement is enforcing a set of orientation constraints on the devices being placed. Such constraints are created in order to, for example, implem...
The sequence-pair was proposed in 1994 as a representation of the packing of rectangles of general structure. Since then, there have been eorts to expand its applicability over s...
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...