Sciweavers

ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
14 years 6 months ago
Dependability Analysis of Nano-scale FinFET circuits
FinFET technology has been proposed as a promising alternative for deep sub-micro bulk CMOS technology, because of its better scalability. Previous work have studied the performan...
Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo
ISVLSI
2006
IEEE
95views VLSI» more  ISVLSI 2006»
14 years 6 months ago
PLAs in Quantum-dot Cellular Automata
Abstract— Research in the fields of physics, chemistry and electronics has demonstrated that Quantum-dot Cellular Automata (QCA) is a viable alternative for nano-scale computing...
Xiaobo Sharon Hu, Michael Crocker, Michael T. Niem...
ISVLSI
2006
IEEE
101views VLSI» more  ISVLSI 2006»
14 years 6 months ago
Nanowire Addressing in the Face of Uncertainty
Eric Rachlin, John E. Savage
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
14 years 6 months ago
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Ko...
ISVLSI
2006
IEEE
114views VLSI» more  ISVLSI 2006»
14 years 6 months ago
A Low Power Lookup Technique for Multi-Hashing Network Applications
Many network security applications require large virus signature sets to be maintained, retrieved, and compared against the network streams. Software applications frequently fail ...
Ilhan Kaya, Taskin Koçak
ISVLSI
2006
IEEE
95views VLSI» more  ISVLSI 2006»
14 years 6 months ago
A Virtual Channel Network-on-Chip for GT and BE traffic
Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. J...
ISVLSI
2006
IEEE
77views VLSI» more  ISVLSI 2006»
14 years 6 months ago
A Robust Synchronizer
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can mor...
Jun Zhou, David Kinniment, Gordon Russell, Alexand...
ISVLSI
2006
IEEE
85views VLSI» more  ISVLSI 2006»
14 years 6 months ago
Variation Aware Placement for FPGAs
Suresh Srinivasan, Narayanan Vijaykrishnan
ISVLSI
2006
IEEE
60views VLSI» more  ISVLSI 2006»
14 years 6 months ago
A new Multilevel Hierarchical MFPGA and its suitable configuration tools
Zied Marrakchi, Hayder Mrabet, Habib Mehrez
ISVLSI
2006
IEEE
89views VLSI» more  ISVLSI 2006»
14 years 6 months ago
System Exploration of SystemC Designs
Due to increasing design complexity new methodologies for system modeling have been established in VLSI CAD. The SystemC methodology gains a significant reduction of design cycle...
Christian Genz, Rolf Drechsler