ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
Contemporary SoC design involves the proper selection of cores from a reference platform. Such selection implies the design exploration of alternative CPUs, which requires the gen...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
This paper presents a quantum algorithm for finding minimal ESCT (Exclusive-or Sum of Complex Terms) or ESOP (Exclusiveor Sum Of Products) expressions for any arbitrary incomplet...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
ISVLSI
2007
IEEE
14 years 6 months ago
2007
IEEE
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...