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33
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ICCAD
1998
IEEE
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ICCAD 1998
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Wireplanning in logic synthesis
14 years 4 months ago
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www.cs.york.ac.uk
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...
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