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ICCAD
1998
IEEE

Wireplanning in logic synthesis

14 years 4 months ago
Wireplanning in logic synthesis
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conventional logic synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose logic synthesis techniques which produce circuits which are "better" for placement. Our proposed approach still separates logic synthesis from physical design.
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1998
Where ICCAD
Authors Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
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