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TCAD
1998
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TCAD 1998
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Gate-level power estimation using tagged probabilistic simulation
13 years 10 months ago
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atrak.usc.edu
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
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