Sciweavers

DAC
1995
ACM
14 years 4 months ago
The Validity of Retiming Sequential Circuits
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Ro...
FPL
2004
Springer
72views Hardware» more  FPL 2004»
14 years 5 months ago
Simultaneous Timing Driven Clustering and Placement for FPGAs
Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement s...
Gang Chen, Jason Cong
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
14 years 6 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong