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    ISCA
    2010
    IEEE
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    The virtual write queue: coordinating DRAM and last-level cache policies
    14 years 4 months ago
    The virtual write queue: coordinating DRAM and last-level cache policies
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    In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
    Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
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