Sciweavers

JOC
2010
92views more  JOC 2010»
13 years 6 months ago
Efficient Cache Attacks on AES, and Countermeasures
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
Eran Tromer, Dag Arne Osvik, Adi Shamir
PC
2007
161views Management» more  PC 2007»
13 years 11 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
ARC
2006
Springer
124views Hardware» more  ARC 2006»
14 years 3 months ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
ICPP
1998
IEEE
14 years 3 months ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang
IPPS
2002
IEEE
14 years 4 months ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
ICCS
2003
Springer
14 years 4 months ago
Exploiting Stability to Reduce Time-Space Cost for Memory Tracing
Memory traces record the addresses touched by a program during its execution, enabling many useful investigations for understanding and predicting program performance. But complete...
Xiaofeng Gao, Allan Snavely
ISCA
2006
IEEE
150views Hardware» more  ISCA 2006»
14 years 5 months ago
Spatial Memory Streaming
Prior research indicates that there is much spatial variation in applications' memory access patterns. Modern memory systems, however, use small fixed-size cache blocks and a...
Stephen Somogyi, Thomas F. Wenisch, Anastassia Ail...
ARC
2010
Springer
144views Hardware» more  ARC 2010»
14 years 6 months ago
QUAD - A Memory Access Pattern Analyser
In this paper, we present the Quantitative Usage Analysis of Data (QUAD) tool, a sophisticated memory access tracing tool that provides a comprehensive quantitative analysis of mem...
S. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, K...