GECCO
2009
Springer
14 years 4 months ago
2009
Springer
New portable consumer embedded devices must execute multimedia applications (e.g., 3D games, video players and signal processing software, etc.) that demand extensive memory acces...
SC
2003
ACM
14 years 4 months ago
2003
ACM
The growing processor/memory performance gap causes the performance of many codes to be limited by memory accesses. If known to exist in an application, strided memory accesses fo...
IEEEPACT
2003
IEEE
14 years 4 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
PARA
2004
Springer
14 years 4 months ago
2004
Springer
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
ACMMSP
2004
ACM
14 years 4 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
WEA
2005
Springer
14 years 4 months ago
2005
Springer
We propose a novel algorithm based on random graphs to construct minimal perfect hash functions h. For a set of n keys, our algorithm outputs h in expected time O(n). The evaluatio...
ICS
2005
Tsinghua U.
14 years 5 months ago
2005
Tsinghua U.
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards. Although several low-power techniques have been proposed,...
ASAP
2005
IEEE
14 years 5 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
ISCAS
2006
IEEE
14 years 5 months ago
2006
IEEE
—As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper...