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MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
14 years 3 months ago
Better Global Scheduling Using Path Profiles
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
Cliff Young, Michael D. Smith
MICRO
1998
IEEE
108views Hardware» more  MICRO 1998»
14 years 3 months ago
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
Chia-Lin Yang, Barton Sano, Alvin R. Lebeck
MICRO
1998
IEEE
98views Hardware» more  MICRO 1998»
14 years 3 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
T. N. Vijaykumar, Gurindar S. Sohi
MICRO
1998
IEEE
89views Hardware» more  MICRO 1998»
14 years 3 months ago
Load Latency Tolerance in Dynamically Scheduled Processors
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
Srikanth T. Srinivasan, Alvin R. Lebeck
MICRO
1998
IEEE
75views Hardware» more  MICRO 1998»
14 years 3 months ago
Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms
This paper evaluates several mechanisms for repairing the return-address stack after branch mispredictions. The return-address stack is a small but important structure for achievi...
Kevin Skadron, Pritpal S. Ahuja, Margaret Martonos...
MICRO
1998
IEEE
102views Hardware» more  MICRO 1998»
14 years 3 months ago
Improving I/O Performance with a Conditional Store Buffer
Lambert Schaelicke, Al Davis
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
14 years 3 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
MICRO
1998
IEEE
92views Hardware» more  MICRO 1998»
14 years 3 months ago
Predictive Techniques for Aggressive Load Speculation
Load latency remains a significant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Pred...
Glenn Reinman, Brad Calder
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
14 years 3 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...