MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading)...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, the additional instruction overhead and addition...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interp...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
— In this paper we investigate mapping stream programs (i.e., programs written in a streaming style for streaming architectures such as Imagine and Raw) onto a general-purpose CP...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
MICRO
2005
IEEE
14 years 5 months ago
2005
IEEE