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DATE
2003
IEEE
108views Hardware» more  DATE 2003»
14 years 5 months ago
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder
In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consum...
Matjaz Verderber, Andrej Zemva, Damjan Lampret