HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder

In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VLD algorithms. Remaining parts were realized in SW with 32bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Matjaz Verderber, Andrej Zemva, Damjan Lampret
• Keywords: DATE 2003, Hardware, MPEG-2 Decoder, MPEG-2 Video Decoder, RISC Processor