Sciweavers

    ISCAS
    2007
    IEEE
    139views Hardware» more  ISCAS 2007»
    VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
    14 years 6 months ago
    VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
    Download  www.ece.rice.edu
    Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
    Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.