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38
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ICCAD
2008
IEEE
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ICCAD 2008
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A polynomial time approximation scheme for timing constrained minimum cost layer assignment
14 years 8 months ago
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www.ece.mtu.edu
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
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