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    ISQED
    2010
    IEEE
    141views Hardware» more  ISQED 2010»
    Assessing chip-level impact of double patterning lithography
    14 years 6 months ago
    Assessing chip-level impact of double patterning lithography
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    —Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
    Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
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