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39
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VTS
1998
IEEE
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VTS 1998
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A Test Pattern Generation Methodology for Low-Power Consumption
14 years 4 months ago
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www.cad.polito.it
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
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