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    VLSID
    2003
    IEEE
    183views VLSI» more  VLSID 2003»
    Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
    14 years 11 months ago
    Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
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    We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
    Vani Prasad, Madhav P. Desai
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